The present invention relates to a charge and discharge control circuit for controlling the charging and discharging of a secondary cell by use of an ON/OFF of a switch circuit, and to a chargeable power supply unit using the circuit.
In the prior art, many chargeable power supply units comprising a secondary cell, a chargeable power supply unit has been disclosed having the construction shown in the circuit block diagram of FIG. 2. This construction is disclosed in Japanese Patent Disclosure H4-75430 entitled, "Chargeable power supply unit" for example. A secondary cell 101 is connected to an external terminal -V0 105 or +V0 104 through a switch circuit 103. A charge and discharge control circuit 102 is connected in parallel to the secondary cell 101. The charge and discharge control circuit 102 has a function of detecting the voltage and current of the secondary cell 102. A charge and discharge inhibiting signal 107 is output from the charge and discharge control circuit 102 so that the switch circuit 103 turns OFF and stops charge current or discharge current in any of the following states: an over-charge state in which the voltage of the secondary cell 101 is higher than the predetermined voltage; an over-discharge state in which the voltage of the secondary cell 101 is lower than another predetermined voltage; and an over-current state in which a current larger than a predetermined current flows through the switch circuit 103 and the voltage of the external terminal +V0 104 reaches a certain voltage. Hereafter, states in which the secondary cell 101 is in over-charge state, an over-discharge state, or a charge or discharge stopping state caused by over-current are respectively referred to as an overcharge protection state, over-discharge protection state, and over-current protection state.
As an another example of a known chargeable power supply unit comprising a secondary cell, a power supply unit having the circuit block diagram shown in FIG. 3 is known. The switch circuit 103 shown in FIG. 2 is connected to the negative side of the secondary cell in series in the circuit, and the operation of the circuit is similar to that of the circuit of FIG. 2.
Generally two FETs (Field Effect Transistor) are used in the switch circuit 103. As an another example of the prior art using the switch circuit, a power supply unit having the circuit block diagram shown in FIG. 4 is known. In FIG. 4, a switch circuit 103 comprises two FETs, operates so as to turn FET-A 112 OFF and to stop discharge current in an over-discharge or over-current state, and operates so as to turn an FET-B 113 OFF and to stop charge current in an over-charge state. Because of that, a signal for controlling the switch circuit is divided into two signals, namely a discharge inhibiting signal 107A and a charge inhibiting signal 107B.
As the prior art having a useful function, a power supply unit like the circuit block diagram shown in FIG. 5 is known as well. In FIG. 5, a charge and discharge control circuit 102 comprises an over-charge detecting circuit 120, an over-discharge detecting circuit 121, an over-current detecting circuit 122, a power down circuit 123, a logic circuit 124, and a delay circuit 129. In FIG. 5, a charger 108 is connected between external terminals +V0 104 and -V0 105, an over-charge detecting signal 130 is output to the logic circuit 124 from the over-charge detecting circuit 120 when the voltage of the secondary cell 101 exceeds the upper limit of charge voltage lasts for a predetermined time. A load 109 is connected between external terminals +V0 104 and -V0 105, an over-discharge detecting signal 131 is output to the logic circuit 124 from the over-discharge detecting circuit 121 when the voltage of the secondary cell 101 exceeds the lower limit of discharge voltage for a predetermined time. An over-current detecting signal 132 is output to the logic circuit 124 from the over-current detecting circuit 122 when the discharge current flowing through the switch circuit 103 exceeds the upper limit and the voltage of the external terminal -V0 105 exceeds the predetermined voltage by ON resistance for a predetermined time. When the over-charge detecting signal 130 is input, the logic circuit 124 outputs the charge inhibiting signal 107B to the FET-B 113 so as to stop charge current. When the over-discharge detecting signal 131 or the over-current detecting signal 132 is input, the discharge inhibiting signal 107A is output to the FET-A 112 so as to stop discharge current.
The over-discharge detecting signal 131 is also output to the power down circuit 123 through the delay circuit 129. As a result, the power down circuit 123 outputs power down signals to each circuit so as to stop the operation of each circuit so that the charge and discharge control circuit 102 does not consume power. Hereafter, the state in which the operation of the charge and discharge control circuit 102 stops is called a power down state. If the charge and discharge control circuit 102 is placed in a power down state once, the charge and discharge control circuit does not open again until a new charge operation starts.
Only when the over-discharge detecting signal 131 is output for the predetermined time, does the delay circuit 129 output the signal to the power down circuit 123. The delay circuit 129 is useful when voltage of the secondary cell 101 falls by over-discharge current, and when an over-current state and an over-discharge state occur at the same time. It means that, in the power supply unit of FIG. 5, the delay circuit 129 stop the over-discharge detecting signal, and inhibits placing the circuit in a power down state, and keeps the charge and discharge control circuit 102 operating for a certain time after the over-current state occurs even in an over-discharge state. The time is determined by forecasting the time that the discharge inhibiting signal 107A stops discharge current. As the over-current protection state stops the flow of discharge current and voltage of the secondary cell 101 thus returns to normal, the over-discharge state is canceled before the delay circuit 129 outputs the over-discharge detecting signal, and starts voltage monitoring again without placing the circuit in a power down state. As the power consumption of the charge and discharge control circuit 102 remains for a certain time even in an over-current protection state, voltage of the secondary cell 101 falls gradually and eventually results in a power down state to stop operation of the charge and discharge control circuit 102.
However in the prior power supply unit constructed as shown in FIG. 5, there has been a problem in that a mistake in the determination of delay time for stopping discharge current causes a malfunction. There has been a problem in that a longer delay time than that which is sufficient for determination is needed than time that discharge current stops and voltage of the secondary cell returns in order to remove malfunction actually. There has been a problem in that the delay circuit 129 is complex and the use of resistors and capacitors makes the circuit large. There has been a problem in that the delay circuit 129 often uses a delay circuit in over-discharge detecting circuit 122 actually, at that case, delay time is needed to determine longer than delay time in over-current detecting circuit 122, and the determination of delay time of over-discharge detecting circuit 121 is limited.
To solve these problems, an object of the present invention is to provide a charge and discharge control circuit using a simple, small circuit, which keeps surely control operation while discharge current flows, voltage of the cell falls, and over-current state and over-discharge state occur at the same time, and stops control operation thereof after stopping instantly discharge current.